1. Field of the Invention
The present invention relates to a voltage regulator capable of suppressing a variation of an output voltage caused when power supply varies.
2. Description of the Related Art
A related-art voltage regulator is now described. FIG. 3 is a circuit diagram illustrating the related-art voltage regulator.
The related-art voltage regulator includes PMOS transistors 106, 107, 108, 301, 302, and 303, NMOS transistors 103, 104, 105, 304, 305, 306, 307, and 308, resistors 109, 110, and 309, a capacitor 310, a ground terminal 100, a power supply terminal 101, and an output terminal 102.
The PMOS transistors 301, 302, and 303, the NMOS transistors 305, 306, and 308, and the resistor 309 form a bias circuit. The NMOS transistors 304 and 307, and the capacitor 310 form a control circuit. The PMOS transistors 106 and 107 and the NMOS transistors 103, 104, and 105 form an error amplifier circuit. The PMOS transistor 108 and the resistors 109 and 110 form an output circuit.
When the voltage regulator is turned on, voltages at both ends of the capacitor 310 become substantially the same so that a gate voltage of the NMOS transistor 304 is raised to a power supply voltage VDD. Then, the NMOS transistor 304 is turned on and a gate voltage of the PMOS transistor 303 is dropped to a ground voltage. Accordingly, the PMOS transistor 303 is turned on to increase a gate voltage of the NMOS transistor 103. Consequently, a current flowing through the NMOS transistor 103 is increased so that an operation speed of the error amplifier circuit is temporarily increased. In this way, neither overshoot nor undershoot, which is caused due to a slow operation speed of the error amplifier circuit, occurs and a negative effect on a circuit connected to a subsequent stage of the output terminal 102 can thus be prevented.
Then, as the capacitor 310 is charged, the gate voltage of the NMOS transistor 304 is dropped. The NMOS transistor 304 is turned off when the gate voltage is dropped to be equal to or less than a threshold Vth. Therefore, an operation of the entire control circuit is stopped. The power supply voltage VDD in this case is in a steady state, and hence the voltage regulator normally operates.
After that, if the power supply voltage VDD suddenly changes, the following operations are performed. Specifically, the capacitor 310 is discharged when the power supply voltage VDD is first dropped, whereas an operating current of the error amplifier circuit is increased by the similar operation described above when the power supply voltage VDD is thereafter increased. Thus, neither overshoot nor undershoot occurs as in the case described above (for example, see Japanese Patent Application Laid-open No. 2001-22455).
However, the related-art voltage regulator has a problem in that the gate voltage of the PMOS transistor 303 is shifted even when the power supply voltage VDD slightly varies. Then, a tail current of the error amplifier circuit is frequently changed and an operating point of the error amplifier circuit is changed, resulting in an unstable operation of the voltage regulator. In addition, the related-art voltage regulator has another problem in that, when the power supply voltage VDD significantly varies, the current of the PMOS transistor 303 is unlimitedly increased to excessively increase the tail current of the error amplifier circuit, resulting in an unstable operation of the voltage regulator.